Functional Verification Flow for an Embedded Microprocessor

Design verification is the process of determining that a design accurately represents the developer´s conceptual description and specifications. These days, design verification represents bring about 60% of total cost of the development of microprocessors or microprocessor cores. A huge number of different activities performed in different stages of the design flow and at different levels of abstraction. Based on the analysis of the structure of an embedded microprocessor, this paper shows the hierarchical verification flow for the microprocessor. The verification flow integrates several verification methods such as coding style checking, register transfer level simulation based on module, system level simulation, virtual machine based verification, timing verification and FPGA based verification. The embedded microprocessor has been successfully fabricated on the SIMC 0.18 μm COMS technology.