Software pipelining and superblock scheduling: compilation techniques for VLIW machines

Compilers for VLIW and superscalar processors have to expose instruction-level parallelism (ILP) to effectively utilize the hardware. Software pipelining is a scheduling technique to overlap successive iterations of loops; and superblock scheduling extracts ILP from frequently executed traces. The authors describe an effort to employ both software pipelining and superblock scheduling techniques in a VLIW compiler. Ten Fortran benchmarks are analyzed, and upon close examination, it appears that both techniques are required to obtain the highest performance across a variety of programs.