FPGA Implementation of low power 64-point radix-4 FFT processor for OFDM system

FFT processor is a crucial block in multi-carrier systems like OFDM (Orthogonal Frequency Division Multiplexing) based Wireless LAN (IEEE 802.11). The portable usage applications of these systems require for low power FFT processor. This paper proposes a radix-4 butterfly architecture using recursive technique for reducing hardware complexity and power consumption using multipliers. A full pipelined architecture design is proposed for constant data throughput for every clock cycle. The FFT processor has been implemented on Xilinxs´ FPGA devices (XCV1000E-8HQ240, X2V3000-6FF1152, X2V6000-6FF1152 and XC2VP30-7FF1152) with device utilization around 35% of the chip, running at an estimated frequency clock 20MHz and with estimated power of 400 mW.