Title :
Process-related reliability issues toward sub-100 nm device regime
Author :
Chang, C.Y. ; Chao, T.S. ; Lin, H.C. ; Chien, C.H.
Author_Institution :
Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
6/24/1905 12:00:00 AM
Abstract :
Crucial process-related reliability issues, such as boron penetration, plasma charging damage, metal-gate processing, and emerging high-k dielectrics, as device scaling progresses towards sub-100 nm technology nodes are discussed in this paper.
Keywords :
ULSI; dielectric thin films; doping profiles; integrated circuit design; integrated circuit interconnections; integrated circuit manufacture; integrated circuit metallisation; integrated circuit reliability; permittivity; plasma materials processing; surface charging; surface treatment; 100 nm; Si:B; ULSI technology; boron penetration; device regime; high-k dielectrics; metal-gate processing; plasma charging damage; process-related reliability; technology nodes; Boron; CMOS technology; Chaos; Degradation; Implants; MOSFET circuits; Plasma materials processing; Plasma temperature; Threshold voltage; Ultra large scale integration;
Conference_Titel :
Microelectronics, 2002. MIEL 2002. 23rd International Conference on
Print_ISBN :
0-7803-7235-2
DOI :
10.1109/MIEL.2002.1003159
