A reconfigurable data-driven multiprocessor architecture for rapid prototyping of high throughput DSP algorithms

A data-driven multiprocessor architecture for the rapid prototyping of complex DSP algorithms, based on direct execution of data-flow graphs, is presented. High computation bandwidth is achieved by exploiting the fine-grain parallelism inherent in the target algorithms using simple processing elements called nanoprocessors interconnected by a configurable static communication network. The use of distributed control and the data-driven execution approach resulted in a highly scalable and modular architecture. A prototype chip, which is currently being designed, contains 64 nanoprocessors, 1 kByte of memory in four banks and eight 16-bit I/O ports, and provides 3.2 GOPS peak when running at 50 MHz. The benchmark results, based on a variety of DSP algorithms in video processing, digital communication, digital filtering and speech recognition, confirm the performance efficiency and generality of the architecture.