The accumulation enhanced emitter switched thyristor - a novel area efficient power semiconductor device

Author

Sweet, M. ; Spulber, O. ; Ngwendson, L. ; Vershinin, K.V. ; De Souza, M.M. ; Narayanan, E. M Sankara

Author_Institution

Emerging Technol. Res. Centre, De Montfort Univ., Leicester, UK

Volume

1

fYear

2002

fDate

6/24/1905 12:00:00 AM

Firstpage

151

Abstract

For the first time, we demonstrate a new power semiconductor device called the accumulation enhanced emitter switched thyristor. The device combines MOS gate control with a thyristor to provide low conduction losses and current saturation at high gate voltages. This device is a volumetric structure which makes use of a floating n well to improve its area efficiency to be greater than that of an EST. The floating n well also forms an accumulation layer and a PMOS that is shown to enhance the on-state and turn-off performance.

Keywords

MOS-controlled thyristors; MOSFET; accumulation layers; losses; MOS gate control; PMOS; accumulation enhanced emitter switched thyristor; accumulation layer; area efficient power semiconductor device; conduction losses; current saturation; floating n well; gate voltages; on-state performance; turn-off performance; volumetric structure; Anodes; Cathodes; Displays; Insulated gate bipolar transistors; MOSFET circuits; Power semiconductor devices; Power semiconductor switches; Semiconductor optical amplifiers; Thyristors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2002. MIEL 2002. 23rd International Conference on

Print_ISBN

0-7803-7235-2

Type

conf

DOI

10.1109/MIEL.2002.1003162

Filename

1003162