Title :
A Parallel Image Processing And Display System (PIPADS): hardware architecture and control software
Author :
Hobbs, Trevor ; Boesen, Brendan ; Kim, Ickseon ; Vance, Colin ; Fraser, Don
Author_Institution :
Dept. of Electr. Eng., New South Wales Univ., Canberra, ACT, Australia
Abstract :
The hardware infrastructure, display system, digital signal processor, array and host-computer control software components developed in a joint project are described. A 64-bit wide implementation of Futurebus+ provides backplane transfer rates of 500 to 700 MByte/s for data flow between array processors, memory, and display modules all being controlled from a host computer workstation. The two million pixel display module supports viewing rates exceeding 36 images per second for single or multiple image streams. Processing is guided by the operator using ball-type or glove-type interactive devices by viewing animation-rate computed images displayed on the screen. One of the hardware modules includes a thirty-two TMS320C40 processor array capable of a peak computation rate of 1.6 GFLOPS and a sustained rate of about 1 GFLOPS on the scan-line oriented algorithms for which the architecture has been optimized.
Keywords :
computer graphic equipment; image processing equipment; interactive devices; parallel architectures; parallel machines; 1 GFLOPS; 1.6 GFLOPS; 2 Mpixel; 500 to 700 MByte/s; 64 bit; Futurebus+; PIPADS; Parallel Image Processing And Display System; TMS320C40 processor array; animation-rate computed images; backplane transfer rates; ball type interactive devices; control software; digital signal processor; glove-type interactive devices; hardware architecture; multiple image streams; scan-line oriented algorithms; viewing rates; Backplanes; Computer architecture; Computer displays; Control systems; Data flow computing; Digital signal processors; Hardware; Image processing; Pixel; Workstations;
Conference_Titel :
System Sciences, 1993, Proceeding of the Twenty-Sixth Hawaii International Conference on
Print_ISBN :
0-8186-3230-5
DOI :
10.1109/HICSS.1993.270754
