Title :
Electrical diagnosis and failure analysis on tree structure circuit
Author :
Ho, Chia-Chi ; Lee, Jeng-Han
Author_Institution :
Yield Enhancement Service Dept., Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan
Abstract :
In this paper, we presented a failure analysis flow for a tree test structure. Such a tree structure has been widely used in many ASIC products for I/O pin test. The case that is introduced is hard to debug by the EMMI methodology. An electrical diagnosis and failure analysis flow was suggested for such a test structure.
Keywords :
application specific integrated circuits; failure analysis; fault location; integrated circuit reliability; integrated circuit testing; network topology; trees (mathematics); ASIC I/O pin test; EMMI debug methodology; electrical diagnosis; emission microscope; failure analysis flow; tree structure circuit; tree test structure; Bonding; Circuit faults; Circuit testing; Clocks; Combinational circuits; Failure analysis; Logic testing; Pins; Switches; Tree data structures;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the
Print_ISBN :
0-7803-8454-7
DOI :
10.1109/IPFA.2004.1345592
