DocumentCode :
1613726
Title :
Wafer-level Hermetic Packaged Dual-axis Digital Microaccelerometer
Author :
Lee, Sangmin ; Kim, Sungwook ; Lee, Sang Chul ; Ko, Hyoungho ; Park, Yonghwa ; Kim, Nam-Kuk ; Cho, Dong-il Dan
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ.
fYear :
2006
Firstpage :
175
Lastpage :
178
Abstract :
A wafer-level hermetic packaged X/Y dual-axis digital microaccelerometer is presented. The MEMS sensing element of the microaccelerometer is fabricated by the sacrificial bulk micromachining (SBM) process. The two microaccelerometers are fabricated on a same silicon substrate, and thus have a perfect orthogonality. To protect the silicon structure of the sensing element, a wafer-level hermetic packaging process is performed. The interface circuit of the microaccelerometer is fabricated using the 0.18 mum CMOS process. The capacitance change of the sensing element is converted to voltage signal by a charge amplifier. The analog signal is converted to digital signal by an A/D converter and a digital filter. The microaccelerometer has the scale factor of 9839 count/g, the output nonlinearity of 0.35 %FSO, the input range of plusmn0.83 g and the bias instability of 2.2965 mg for the x-axis, and the scale factor of 10087 count/g, the output nonlinearity of 0.38 %FSO, the input range of plusmn0.81 g and the bias stability of 7.1881 mg for the y-axis
Keywords :
CMOS integrated circuits; accelerometers; amplifiers; analogue-digital conversion; digital filters; micromachining; microsensors; wafer level packaging; A/D converter; CMOS process; MEMS sensing element; SBM process; X/Y dual-axis digital microaccelerometer; bias instability; charge amplifier; digital filter; interface circuit fabrication; output nonlinearity; sacrificial bulk micromachining; scale factor; silicon substrate; wafer-level hermetic package; CMOS process; Capacitance; Circuits; Micromachining; Micromechanical devices; Packaging; Protection; Silicon; Voltage; Wafer scale integration; Dual-axis microaccelerometer; SBM (Sacrificial Bulk Micromachining); Wafer-level hermetic packaging;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SICE-ICASE, 2006. International Joint Conference
Conference_Location :
Busan
Print_ISBN :
89-950038-4-7
Electronic_ISBN :
89-950038-5-5
Type :
conf
DOI :
10.1109/SICE.2006.315396
Filename :
4108819
Link To Document :
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