Design of compact high-frequency output buffer for testing of analog CMOS VLSI circuits

Author

VanPeteghem, P.M. ; Duque-Carrillo, J.F. ; Liu, Haoyang Haven

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

fYear

1989

Firstpage

167

Abstract

A compact high-frequency CMOS analog buffer for testing purposes is presented. A prototype integrated in a 3-μm CMOS process drives a 15-pF, 10-kΩ load and shows a bandwidth of 25 MHz, a large-signal setting time to 1% of less than 90 ns, and a dynamic range over 77 dB. Power consumption is 2.4 mA per cell. Its small size (less than 0.18 mm ²) makes it suitable for monitoring low-capacitance internal nodes of analog or mixed-mode VLSI circuits

Keywords

CMOS integrated circuits; VLSI; analogue circuits; buffer storage; integrated circuit testing; linear integrated circuits; 10 kohm; 15 pF; 2.4 mA; 25 MHz; 3 micron; 90 ns; CMOS process; analog CMOS VLSI circuit testing; analog VLSI circuits; compact high-frequency output buffer design; dynamic range; large-signal setting time; low capacitance internal node monitoring; mixed-mode VLSI circuits; power consumption; prototype output buffer; small size; Bandwidth; CMOS analog integrated circuits; CMOS process; Capacitance; Circuit testing; Dynamic range; Energy consumption; Operational amplifiers; Transconductance; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1989., IEEE International Symposium on

Conference_Location

Portland, OR

Type

conf

DOI

10.1109/ISCAS.1989.100318

Filename

100318