Title :
ESD protection design for high-speed I/O interface of stub series terminated logic (SSTL) in a 0.25-μm salicided CMOS process
Author :
Ker, Ming-Dou ; Chuang, Che-Hao
Author_Institution :
Nanoelectron. & Gigascale Syst. Lab., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
Abstract :
ESD protection design for high-speed I/O interface of stub series terminated logic (SSTL) is proposed. The SSTL I/O buffer with the proposed ESD protection design, which is designed to operate with a clock of 400 MHz, has been fabricated and verified in a 0.25-μm salicided CMOS process. The human-body-model (HBM) and machine-model (MM) ESD levels of this SSTL I/O buffer can be greater than 8 kV and 750 V, respectively. Based on the excellent ESD performance, one set of area-efficient I/O cell library for SSTL in 1.8 V applications with this ESD protection design has been built up in a 0.25-μm salicided CMOS process.
Keywords :
CMOS logic circuits; circuit CAD; electrostatic discharge; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; integrated circuit modelling; integrated circuit reliability; logic CAD; protection; 0.25 micron; 1.8 V; 400 MHz; 750 V; 8 kV; ESD performance; ESD protection design; HBM; MM; SSTL I/O buffer; area-efficient I/O cell library; clock; high-speed I/O interface; human-body-model ESD levels; machine-model ESD levels; salicided CMOS process; stub series terminated logic; Atherosclerosis; CMOS logic circuits; CMOS process; Electrostatic discharge; Frequency; Logic design; MOS devices; Protection; Stress; Variable structure systems;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the
Print_ISBN :
0-7803-8454-7
DOI :
10.1109/IPFA.2004.1345600
