Design of a 32-bit fully asynchronous microprocessor (FAM)

Author

Cho, Kyoung-Rok ; Okura, Kazuma ; Asada, Kunihiro

Author_Institution

Semicond. Lab., RIST, Hyoja-dong Pohang City, South Korea

fYear

1992

Firstpage

1500

Abstract

The authors describe a 32-b fully asynchronous microprocessor (FAM) with the four-stage pipeline based on a reduced instruction set computing (RISC)-like architecture. Issues relevant to the processor such as design of the self-timed data path, the asynchronous controller and interconnection circuits are discussed. The FAM showed an average operation speed of 3.5 ns for each instruction on 0.5-μm CMOS technology. Simulation results are included using parameters extracted from the layout

Keywords

CMOS integrated circuits; microprocessor chips; pipeline processing; reduced instruction set computing; 0.5 micron; 3.5 ns; 300 MIPS; 32 bit; CMOS technology; asynchronous controller; four-stage pipeline; fully asynchronous microprocessor; interconnection circuits; reduced instruction set computing; self-timed data path; CMOS technology; Circuit simulation; Computational modeling; Computer architecture; Data mining; Integrated circuit interconnections; Microprocessors; Pipelines; Process design; Reduced instruction set computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on

Conference_Location

Washington, DC

Print_ISBN

0-7803-0510-8

Type

conf

DOI

10.1109/MWSCAS.1992.271009

Filename

271009

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1613924