High Performance Algorithm for Twiddle Factor of Variable-size FFT Processor and its Implementation

This paper presents a new storage and address accessing scheme of twiddle factors based on Multi-bank memory architecture. It makes the three twiddle factors needed by a mixed-radix 4/2 butterfly operation can be accessed simultaneously. It also makes it possible to design a variable-size FFT processor with only one three-bank twiddle factor lookup table which is advantageous over those other existing algorithms that need double of it. The algorithm proposed can be implemented with only one shift register and an accumulator. In addition, the access number of one of the three banks and its size are reduced by half. Therefore, its implementation is low complexity and area saving.