A Novel Technique for Efficient Hardware Simulation of Spatiotemporally Correlated MIMO Fading Channels

We present a fading model with a compact and fast hardware implementation suitable for correlated Rayleigh fading channel simulators. The proposed scheme is based on the sum-of-sinusoids model because of its flexibility and efficient mapping onto hardware. Using numerical simulation, it is shown that the statistical properties of the generated fading variates match the theoretical reference model. Since the cross-correlations between sequences of generated fading variates are small, this model can also be used to implement a time-correlated multiple-input multiple-output (MIMO) fading channel simulator on a single field-programmable gate array (FPGA). The MIMO channel simulator can also be extended to support spatial correlation between generated fading samples. An implementation of a spatiotemporally correlated (4, 4) MIMO channel simulator on a Xilinx Virtex-II Pro XC2VP100-6 FPGA uses 46% of the configurable slices, 30% of the dedicated multipliers, and 32% of the on-chip block memories while generating 4 times 201 million 2 times 16-bit complex-valued fading samples per second.