Title :
Single-event-induced barrier lowering in deep-submicron MOS devices and circuits
Author :
Jain, Palkesh ; Vasi, J. ; Lal, Rakesh
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Mumbai, India
Abstract :
In this paper, we report a novel reliability issue, coined single-event-induced barrier lowering (SEBL), which deals with barrier lowering along the channel and the source-substrate junction during a single event high energy particle strike on MOS devices. We have comprehensively studied SEBL for different channel lengths and our results suggest that it can cause significant charge enhancement, and therefore can bring down the critical energy to low values. Thus SEBL can be a strong deterrent to further reduction of the stored charge on a node and can have serious scaling implications.
Keywords :
MOSFET; radiation effects; semiconductor device reliability; MOS circuits; MOS device reliability; NMOS transistor; SEBL; SRAM; channel length; charge enhancement; critical energy lowering; node stored charge reduction; scaling; short channel transistors; single event high energy particle strike; single-event-induced barrier lowering; Alpha particles; Circuit simulation; Logic devices; MOS devices; Microelectronics; Neutrons; Protons; Random access memory; Single event upset; Space technology;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the
Print_ISBN :
0-7803-8454-7
DOI :
10.1109/IPFA.2004.1345627
