Title :
Simulation and Analysis of DS-SS Anti-jamming Performance Based on VHDL
Author :
Qu, Xia ; Li, Wenjie
Author_Institution :
Sch. of Inf. Sci. & Eng., Changzhou Univ., Changzhou, China
Abstract :
Arming at the difficulty of traditional simulation method to achieve analysis of DD-SS Anti-jam capability in engineering area and the implementation complexity using pure hardware, the paper introduces a simulation scheme based on VHDL. Two different spread spectrum gain systems are designed. The noise is recommended to the spread spectrum signal which characterizes manufacture under various interference. Search and acquisition by sequence phase method is adopted to complete the synchronization and to accomplish correlation despreading. Through increasing gradually noise in two spreading gain systems respectively, anti-jam performance of the system is analysised under different interference environment. Simulation result shows that increasing spreading gain can improve anti-jam capability. When spread spectrum gain is 127, the system can despread correctly by 26% bit error rate of received spread spectrum signal. If Spread spectrum gain increases 3 dB, the system despreads with zero error code even by 38% bit error rate of received signal. The simulation method and the conclusion have some reference value for the actual application.
Keywords :
code division multiple access; communication complexity; correlation theory; error statistics; hardware description languages; radiofrequency interference; spread spectrum communication; synchronisation; VHDL-based DS-SS antijamming performance; bit error rate; correlation despreading; engineering area; implementation complexity; interference environment; sequence phase method; simulation method; spread spectrum gain; spread spectrum gain systems; zero error code; Analytical models; Bit error rate; Gain; Interference; Noise; Spread spectrum communication; Synchronization; Anti-jam capability; Correlation despreading; Direct sequence spread spectrum communication system; Search and acquisition by sequence phase; Very-High-Speed Integrated Circuit Hardware Description Language;
Conference_Titel :
Industrial Control and Electronics Engineering (ICICEE), 2012 International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4673-1450-3
DOI :
10.1109/ICICEE.2012.306