Title :
Over one million TPCC with a 45nm 6-core Xeon® CPU
Author :
Kuppuswamy, Ravi ; Sawant, Shankar R. ; Balasubramanian, Srikanth ; Kaushik, Pradeep ; Natarajan, Narayanan ; Gilbert, Jeffrey D.
Author_Institution :
Intel, Bangalore, India
Abstract :
This paper describes the 6-core Xeonreg 7400 series processor family, code-name Dunnington, designed for a broad range of highly power efficient servers. The processor consists of three dual-core 45nm CoreTM processors and a shared inclusive 16 MB L3 cache (LLC) integrated on a monolithic 503 mm2 die. The system interface is FSB based with the l/Os incorporated into the center of the die. The core-to-FSB connection is replaced with an on-die low-latency uncore interface. The uncore arbitrates among core, LLC, and external bus requests. The processor has 1.9 B transistors and is implemented in 45nm CMOS using high-kappa metal-gate transistors and nine copper interconnect layers. The maximum thermal design power is 130 W.
Keywords :
CMOS digital integrated circuits; high-k dielectric thin films; microprocessor chips; 16 MB L3 cache; 6-core Xeon CPU; Dunnington; TPCC benchmark; Xeonreg 7400 series processor family; core-to-FSB connection; dual-core processors; high-kappa metal-gate transistors; interconnect layers; monolithic die; power 130 W; size 45 nm; uncore interface; Built-in self-test; CMOS technology; Clocks; Delay; Design for testability; Frequency; Logic; Packaging; Phase locked loops; Timing;
Conference_Titel :
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-3458-9
DOI :
10.1109/ISSCC.2009.4977312
