DocumentCode
1614584
Title
A 12b 2.9GS/s DAC with IM3 ≪−60dBc beyond 1GHz in 65nm CMOS
Author
Lin, C.-H. ; van der Goes, F. ; Westra, J. ; Mulder, J. ; Lin, Y. ; Arslan, E. ; Ayranci, E. ; Liu, X. ; Bult, K.
Author_Institution
Broadcom, Irvine, CA, USA
fYear
2009
Firstpage
74
Abstract
A 12 b 2.9 GS/S current-steering DAC implemented in 65 nm CMOS is presented, with an IM3 <-60 dBc beyond 1 GHz while driving a 50 Omega load with an output swing of 2.5 Vpp-diff and dissipating a power of 188 mW. The SFDR measured at 2.9 GS/S is better than 60 dB beyond 340 MHz.
Keywords
CMOS integrated circuits; digital-analogue conversion; CMOS; SFDR measurement; current-steering DAC; power 188 mW; power dissipation; size 65 nm; word length 12 bit; Clocks; Decoding; Ethernet networks; Frequency conversion; Frequency measurement; Impedance; Linearity; Signal design; Solid state circuits; Switching converters;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location
San Francisco, CA
Print_ISBN
978-1-4244-3458-9
Type
conf
DOI
10.1109/ISSCC.2009.4977314
Filename
4977314
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