Title :
A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS
Author :
Alpman, Erkan ; Lakdawala, Hasnain ; Carley, L. Richard ; Soumyanath, K.
Author_Institution :
Intel, Hillsboro, OR, USA
Abstract :
High-speed medium-resolution ADCs are widely utilized in high-speed communication systems, such as serial links, UWB, and OFDM-based 60 GHz receivers. Due to complex DSP and low-power constraints, digital basebands are designed in low-leakage, high-VT low-power (LP) CMOS processes making the design of high-speed ADCs challenging. Time-Interleaved (Tl) successive-approximation-register-based (SAR) ADCs are ideally suited to these applications due to their highly scalable architecture and due to the steady improvement in matching and density of metal-finger capacitors (MFC). This paper presents a Tl C-2C SAR ADC that achieves high performance by using: (1) a small-area C-2C SAR architecture with low input capacitance; (2) high-speed boosted switches to overcome high device threshold; (3) background comparator offset calibration and radix calibration; and (4) redundant-ADC-based gain, offset and timing calibration to reduce Tl errors.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; low-power electronics; C-2C SAR ADC; analog-digital convertor; comparator offset calibration; high-speed boosted switches; high-speed communication system; low input capacitance; low-power digital CMOS process; metal-finger capacitors; power 50 mW; radix calibration; size 45 nm; time-interleaved successive-approximation-register; voltage 1.1 V; word length 7 bit; Baseband; CMOS process; Calibration; Capacitance; Capacitors; Digital signal processing; Performance gain; Process design; Switches; Timing;
Conference_Titel :
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-3458-9
DOI :
10.1109/ISSCC.2009.4977315
