Title :
A 10b 500MHz 55mW CMOS ADC
Author :
Verma, Ashutosh ; Razavi, Behzad
Author_Institution :
Univ. of California, Los Angeles, CA, USA
Abstract :
Recent work on ADCs targeting sampling rates of hundreds of MHz with resolutions in the range of 10 to 11 b has faced speed limitations with a single channel or employed interleaving, but with a relatively high power dissipation or low SNDR. This paper introduces a calibration technique that, together with a high-speed opamp topology, allows a single channel to operate at 500 MHz and digitize a 233 MHz input with an SNDR of 53 dB. This SNDR yields a figure of merit (FOM) of 0.3 pJ/conversion-step, the lowest reported for 10 and 11 b ADCs running at these frequencies.
Keywords :
CMOS integrated circuits; analogue-digital conversion; calibration; high-speed integrated circuits; operational amplifiers; CMOS ADC; SNDR; calibration technique; figure-of-merit; frequency 233 MHz; frequency 500 MHz; high-speed opamp topology; power 55 mW; word length 10 bit; CMOS technology; Calibration; Capacitors; Circuits; Energy consumption; Frequency; Least squares approximation; Linearity; Sampling methods; Testing;
Conference_Titel :
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-3458-9
DOI :
10.1109/ISSCC.2009.4977319
