A design for testability method using RTL partitioning

Author

Hosokawa, Toshinori ; Kawaguchi, Kenichi ; Ohta, Mitsuyasu ; Muraoka, Michiaki

Author_Institution

Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Osaka, Japan

fYear

1996

Firstpage

88

Lastpage

93

Abstract

We will present a Design For Testability (DFT) method on Register Transfer Level (RTL). In our method RTL circuits are partitioned into some testable blocks, and each of the blocks is isolated by using primary pins and additional multiplexers so that automatic test pattern generation (ATPG) can be applied for each of the blocks. The experimental results for some RTL circuits designed with Bchart show that our method reduces the number of test patterns from a seventeenth to an eightieth and 10 to 30% of area overhead for test circuits in comparison with a full scan design method

Keywords

automatic testing; design for testability; integrated circuit testing; large scale integration; logic CAD; logic partitioning; logic testing; Bchart; RTL partitioning; additional multiplexers; area overhead; automatic test pattern generation; design for testability method; primary pins; register transfer level; testable blocks; Automatic test pattern generation; Central Processing Unit; Circuit faults; Circuit testing; Design for testability; Design methodology; Large scale integration; Pins; Registers; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1996., Proceedings of the Fifth Asian

Conference_Location

Hsinchu

ISSN

1085-7735

Print_ISBN

0-8186-7478-4

Type

conf

DOI

10.1109/ATS.1996.555142

Filename

555142