A 16b 125MS/s 385mW 78.7dB SNR CMOS pipeline ADC

Today´s communication systems require high-performance low-cost ADCs with emphasis on low power, and the ability to IF-sample to reduce receiver complexity. Further, the often-overlooked metric of small-signal linearity quantified by SFDR for less-than-full-scale inputs is important, especially in the presence of large interferers. This 16 b pipeline ADC achieves 78.7 dB SNR, 78.6 dB SNDR and 96 dB SFDR at 125 MS/s with a 30 MHz input, while dissipating 385 mW from a 1.8 V supply. The ADC quantizes inputs up to 150 MHz with an SNR >76 dB and an SFDR >85 dB, has a jitter of 65 fs and accepts 2 V_pp-diff, inputs. Further, with dithering enabled the worst spur is <-98 dB for inputs below -4 dBFS at 100 MHz IF. The ADC is fabricated in a 1P5M 0.18mum CMOS process.