• DocumentCode
    1614795
  • Title

    Subharmonically injection-locked PLLs for ultra-low-noise clock generation

  • Author

    Jri Lee ; Huaide Wang ; Wen-Tsao Chen ; Yung-Pin Lee

  • Author_Institution
    Nat. Taiwan Univ., Taipei, Taiwan
  • fYear
    2009
  • Firstpage
    92
  • Abstract
    High-speed low-noise clocks are essential in numerous applications. In this paper, complete analysis and validation of subharmonic injection locking that can substantially reduce the PLL phase noise at negligible cost is presented. Two 20 GHz PLLs based on this technique demonstrate 149 and 85 fsrms jitter while consuming 38 and 105mW, respectively.
  • Keywords
    clocks; injection locked oscillators; jitter; phase locked loops; phase noise; PLL jitter; PLL phase noise; frequency 20 GHz; high-speed low-noise clock generation; power 105 mW; power 38 mW; subharmonically injection-locked PLL; Circuits; Clocks; Energy consumption; Frequency; Injection-locked oscillators; Jitter; Phase locked loops; Phase noise; Pulse generation; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    978-1-4244-3458-9
  • Type

    conf

  • DOI
    10.1109/ISSCC.2009.4977323
  • Filename
    4977323
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1614795