Title :
VLSI RNS implementation of fast IIR filters
Author :
Cardarilli, G.C. ; Lojacono, R. ; Salerno, M. ; Sargeni, E.
Author_Institution :
Dept. of Electron. Eng., Rome Univ., Italy
Abstract :
A residue number system (RNS) method to implement fast recursive digital filters is considered. The speed improvement is obtained as a better performance of the elementary arithmetic blocks, given by the RNS. In the past the RNS double moduli method has been applied as a scaling procedure. In the present work a technique which uses this method partially is presented to improve the performance of recursive filters. This technique is based on the Chinese remainder theorem (CRT). Using CRT a partially parallelized structure can be realized which reduces the computational time and improves the speed performance. The effectiveness of this method has been tested numerically and by a 1.5-μm CMOS implementation of a second order infinite impulse response (IIR) filter cell
Keywords :
CMOS integrated circuits; VLSI; digital arithmetic; digital filters; digital integrated circuits; CMOS implementation; Chinese remainder theorem; VLSI RNS implementation; computational time; fast IIR filters; partially parallelized structure; performance; recursive digital filters; Arithmetic; CMOS image sensors; Cathode ray tubes; Digital filters; IIR filters; Pipelines; Quantization; Signal processing algorithms; Testing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-0510-8
DOI :
10.1109/MWSCAS.1992.271046
