Modeling CMOS Gates Using Equivalent Inverters

In this paper a complete approach for timing and power modeling and characterization of the CMOS gates is proposed. At first, a simplified but still accurate transistor current model is proposed taking into account the nanoscale effects which have a countable effect on the circuit behavior. Using the expressions of the transistor current, the differential equation which describes the operation of the CMOS inverter is solved analytically and expressions for the output voltage and supply current and thus for propagation delay and the power consumption are derived. These expressions are parametric according the input signal slew, output load, transistor widths, supply voltage, temperature and process. Complex gates are replaced by equivalent inverters with similar behavior and the expressions developed for the inverter are employed. Parametric expressions are derived for the transistor widths of the equivalent inverters using a fitting procedure. Results for the NAND and NOR gates show that the proposed approach presents a sufficient accuracy with an average error in propagation delay at 5%.