DocumentCode :
1614889
Title :
High density 3D through silicon stacking manufacturing readiness and challenges
Author :
Nowak, Marcjan
fYear :
2010
Firstpage :
108
Lastpage :
108
Abstract :
Cost reduction, thermal management, design, and DFT have been described as the "4 horsemen of the Apocalypse for 3D ICs" (P. Garrou, Semiconductor International, PFLE, Oct 16, 2009). While specific 3D thermal management techniques and DFT solutions are likely to remain proprietary to each company, the industry can tame the cost reduction and design beasts by collaborating on common tools, formats, and standards. Cost targets and cost reduction opportunities for 3D high density TSS technology will be described. Standards for the manufacturing supply chain, and for design data formats and associated input data, will be proposed. Taming these challenges will enable effective design and manufacturing supply chains for high density TSS.
Keywords :
cost reduction; design for testability; electronics industry; silicon; supply chain management; thermal management (packaging); 3D high density TSS technology; 3D thermal management techniques; DFT solutions; cost reduction; cost targets; design data formats; high density 3D through silicon stacking manufacturing; manufacturing supply chain;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Semiconductor Manufacturing Conference (ASMC), 2010 IEEE/SEMI
Conference_Location :
San Francisco, CA
ISSN :
1078-8743
Print_ISBN :
978-1-4244-6517-0
Type :
conf
DOI :
10.1109/ASMC.2010.5551428
Filename :
5551428
Link To Document :
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