An optimal test sequence for the JTAG/IEEE P1149.1 test access port controller

Author

Dahbura, Anton T. ; Uyar, M. Ümit ; Yau, Chi W.

Author_Institution

AT&T Bell Lab., Murray Hill, NJ, USA

fYear

1989

Firstpage

55

Lastpage

62

Abstract

A test sequence is given for the test access port (TAP) controller portion of the boundary-scan architecture proposed by the Joint Test Action Group (JTAG) and IEEE Working Group P1149.1 as an industry-standard design-for-testability technique. The resulting test sequence, generated by using a technique based on Rural Chinese Postman tours and unique input/output sequences, is of minimum cost (time) and rigorously tests the specified functional behavior of the controller. The test sequence can be used for detecting design faults for conformance testing or for detecting manufacture-time/run-time defects/faults

Keywords

automatic test equipment; automatic testing; computer architecture; computer interfaces; fault location; logic testing; standards; ATE; IEEE Working Group; JTAG/IEEE P1149.1 test access port controller; Joint Test Action Group; Rural Chinese Postman tours; boundary-scan architecture; conformance testing; cost; design faults; design-for-testability; functional behavior; industry-standard; input/output sequences; manufacture-time/run-time defects/faults; optimal test sequence; Circuit faults; Circuit testing; Controllability; Design engineering; Fault detection; Integrated circuit testing; Logic; Manufacturing; Optimal control; Semiconductor device testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1989. Proceedings. Meeting the Tests of Time., International

Conference_Location

Washington, DC

Type

conf

DOI

10.1109/TEST.1989.82277

Filename

82277