DocumentCode
1615007
Title
Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit
Author
Terada, Jun ; Ohtomo, Yusuke ; Nishimura, Kazuyoshi ; Katsurai, Hiroaki ; Kimura, Shunji ; Yoshimoto, Naoto
Author_Institution
NTT, Atsugi
fYear
2009
Firstpage
104
Abstract
In this paper, a burst-mode CDR circuit is presented that achieves output-data- jitter reduction of 3dB at jitter frequency of 1 GHz, synchronization to the input data within 14 bits of the burst input, and tolerance to pulse-width distortion (PWD) of +0.22/-0.32UI at 10.3125 Gb/s operation. These characteristics are provided by a CDR architecture with jitter-reduction and PWD-compensation circuits.
Keywords
clock and data recovery circuits; jitter; optical fibre networks; voltage-controlled oscillators; bit rate 10 Gbit/s; bit rate 10.3125 Gbit/s; burst-mode CDR circuit; delta-sigma DAC; frequency 1 GHz; gated VCO; jitter reduction; pulse-width-distortion compensation circuits; Clocks; Detectors; Frequency; Injection-locked oscillators; Jitter; Optical buffering; Optical receivers; Pulse circuits; Varactors; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location
San Francisco, CA
Print_ISBN
978-1-4244-3458-9
Type
conf
DOI
10.1109/ISSCC.2009.4977329
Filename
4977329
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