VLSI-suited solution of linear systems

One- and two-dimensional processor arrays for the orthogonal solution of systems of linear equations are presented. The arrays execute the orthogonal Faddeeva algorithm, and each processor cell is able to carry out a square-root and division-free Givens rotation (GR). Contrary to all previous approaches for orthogonal linear system solvers, the processor arrays have the following advantages: only four multipliers and two adders in each processor cell; almost full utilization of these hardware components (asymptotically 100%); and reduction of latency time from O(b) to O(log b) for one GR, where b is the number of bits