Minimizing testing time in scan-path architecture

In general test pattern generators attempt to generate a minimum number of test vectors to detect all or most detectable faults for a given fault model. It is implicitly assumed that the individual test vectors of the test set are applied in parallel. In the boundary scan technique the test vectors are typically shifted serially to the scan register to stimulate the logic circuit. Therefore, O(nT ) clock cycles are needed to apply the test set serially, where n is the number of inputs of the logic circuit and T is the number of test vectors in the test set. The authors present a heuristic algorithm to reduce the length of the bit sequence that is shifted serially to generate a given test set. They show the results obtained for randomly generated test sets. The percentage reduction in testing time is computed