Yield enhancement through silicon Epi defect reduction

Defects and the yield loss associated with them have plagued semiconductor fabs since the dawn of the industry. Research has shown that contamination is responsible for up to 75% of the yield loss in integrated circuit fabrication. A single defect can destroy an entire die by creating a short in a junction region or cause an open circuit in a gate electrode of a device. Defects can also degrade device performance and reliability by generating undesirable localized fields or creating leakage paths. For many devices, the epi deposition layer is the first process step onto the raw silicon substrate and defectivity within the layer will negate all process steps thereafter. This article will begin by introducing the broad range of epi defects including stacking faults, spikes, scratches, and particles including a discussion on the theoretical root causes of those defects. A description of the International Rectifier´s Epi Services facility and their standard process flow will also be provided. IR Epi Services provides epi wafers both to internal International Rectifier factories, as well as to external customers. End of line yield of the product from IR Epi Services suffered primarily in the drain saturation current when the gate-source voltage equals 0 (IDSS). Chart 1 presents historical IDSS data for a typical quarter versus the aggressive long term goal of a 2X improvement in yield as assigned by the internal IR Yield Enhancement Engineering Team for the major product families running in the fab. IR Epi Services had to improve their product´s device yield in order to maintain long-term relevancy. A major Six Sigma DMAIC (Define, Measure, Analyze, Improve, Control) project, led by a Six Sigma Blackbelt, was organized to evaluate and improve the process. A brief definition of the DMAIC methodology will be given and then the remaining bulk of the paper will describe the steps to improve IR Epi Service´s process to meet their customer´s requirements. The Definition of- - the problem statement, as already stated, is elevated IDSS yield loss. Literature provides that defects, such as stacking faults, provide a path for the leakage current IDSS. Therefore, IR Epi Services had to improve their defect levels in order to improve their product´s performance. IR Epi Services Measured particles in three different ways: bright-light inspection, microscopic inspection, and automated laser diffraction metrology. The paper will describe the limitations of these techniques and offer a solution for those limitations. By Analyzing this solution, a very strong correlation was developed that showed post epi defectivity measurements using automated metrology at the proper detection levels could predict IDSS yield. Using the correlation shown in Chart 2, IR Epi Services was able to implement tight outgoing guard-band limits, which were actually tighter than customer specification limits. Initially, IR Epi Services witnessed large internal whole wafer scrap losses due to the tighter outgoing defect criteria as shown in Chart 3. Over several quarters, IR Epi Services worked to improve their internal yield by addressing multiple areas within their process. These areas included Facilities, Operations, Engineering, and Maintenance. A fishbone diagram will be provided discussing each area´s improvement opportunities and those improvements will also be detailed. Once the improvements were made, it was vital for IR Epi Services to Control their process. The methodologies used to maintain the particle performance of outgoing product will be described in detail. Examples of the control methodology include real-time Statistical Process Control (SPC) of all outgoing particle measurements on product and weekly reactor trending reports using raw metrology data. The results of the improvement are conclusive and Chart 4 illustrates that IR Epi Services was able to improve their wafer processing significantly to meet their customer´s yield expectations. The yield