Title :
SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic
Author :
Kostin, Sergei ; Raik, Jaan ; Ubar, Raimund ; Jenihhin, Maksim ; Copetti, Thiago ; Vargas, Fabian ; Bolzani Poehls, Leticia
Author_Institution :
Tallinn Univ. of Technol., Tallinn, Estonia
Abstract :
Accurate prediction of circuit aging is essential to reliable design, in particular for critical applications. Based on intensive HSPICE electrical simulations, we developed a predictive model to compute NBTI-induced path delay degradation at gate-level. The method is based on a static timing analysis that computes path delay under NBTI-induced VTHp (pMOS transistor threshold voltage) degradation. The proposed approach is demonstrated on an industrial ALU circuit design. The obtained results demonstrate a good fitting between the developed model and HSPICE simulations with several orders of magnitude gain in simulation speed.
Keywords :
MOSFET; SPICE; integrated circuit design; logic circuits; negative bias temperature instability; NBTI-induced path delay degradation; SPICE-inspired fast gate-level computation; accurate prediction; circuit aging; industrial ALU circuit design; intensive HSPICE electrical simulations; nanoscale logic; pMOS transistor threshold voltage; predictive model; static timing analysis; Aging; Degradation; Delays; Integrated circuit modeling; Logic gates; MOSFET; SPICE; NBTI-induced path delay estimation; Negative Bias Temperature Instability (NBTI); aging; logic circuit; predictive model; static timing analysis;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2015 IEEE 18th International Symposium on
Conference_Location :
Belgrade
Print_ISBN :
978-1-4799-6779-7
DOI :
10.1109/DDECS.2015.53
