Title :
1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture
Author :
Moon, Yongsam ; Cho, Yong-Ho ; Lee, Hyun-Bae ; Jeong, Byung-Hoon ; Hyun, Seok-Hun ; Kim, Byung-Chul ; Jeong, In-Chul ; Seo, Seong-Young ; Shin, Jun-Ho ; Choi, Seok-Woo ; Song, Ho-Sung ; Choi, Jung-Hwan ; Kyung, Kye-Hyun ; Jun, Young-Hyun ; Kim, Kinam
Author_Institution :
Samsung Electron., Hwasung
Abstract :
As the workload and speed of a computer system increase, both the data bandwidth and capacity of main memory inevitably need to grow. However, the number of slots per channel is limited to maintain high bandwidth, making the capacity requirement difficult to meet. Another problem is that computer systems impose a limit on the supply of power since their power dissipation increases rapidly where main memories account for roughly 15% of total power consumption. To address these issues, we design a 4Gb DDR3 SDRAM that supports a 1.2 V supply voltage and 1.6 Gb/s data rate.
Keywords :
DRAM chips; amplifiers; DDR3 SDRAM; bit rate 1.6 Gbit/s; computer system; data bandwidth; hybrid-I/O sense amplifier; memory capacity; power consumption; power dissipation; segmented subarray architecture; size 56 nm; storage capacity 4 Gbit; voltage 1.2 V; CMOS logic circuits; Clocks; Counting circuits; Delay effects; Flip-flops; Random access memory; SDRAM; Semiconductor device measurement; Solid state circuits; Voltage;
Conference_Titel :
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-3458-9
DOI :
10.1109/ISSCC.2009.4977341