A Delay Measurement Mechanism for Asynchronous Circuits of Bundled-Data Model

In this paper, we propose a delay measurement mechanism for asynchronous circuits of bundled-data model. In the proposed method, a time to digital converter (TDC) is used as a mechanism to measure the delay of a combinational block. Specifically, the critical paths of the combinational block are sought and their outputs are connected to the TDC to measure the delay of the block. Transitions which will be measured by the TDC are propagated through the paths using path delay tests for the paths. To evaluate the effectiveness of the proposed method, for a sample circuit, the delay margin of the circuit is evaluated by the TDC using logic simulation with timing information.