Title :
New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams
Author :
Jasnetski, Artjom ; Raik, Jaan ; Tsertov, Anton ; Ubar, Raimund
Author_Institution :
Testonica Lab. OU, Tallinn, Estonia
Abstract :
The paper presents a novel approach to high-level fault modeling and test generation for microprocessors using High-Level Decision Diagrams (HLDD). A general frame-work and novel techniques for automated software-based self-test program generation are discussed. On this basis new previously not published test quality improvement capabilities of the approach are high-lighted and explained. Based on the high level fault model defined for HLDDs a novel class of hard-to-test faults, called "unintended actions", is proposed. In addition, the mechanisms for reducing the risk of fault masking is explained. The experimental results show the superiority of the new method by achieving a higher quality of tests with shorter length compared to the previous results.
Keywords :
automatic test pattern generation; built-in self test; decision diagrams; fault diagnosis; microprocessor chips; fault masking; fault models; high-level decision diagrams; microprocessors; self-test generation; Automatic test pattern generation; Built-in self-test; Circuit faults; Logic gates; Microprocessors; Registers; high-level decision diagrams; microprocessor; software-based self-test (SBST); test program generation;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2015 IEEE 18th International Symposium on
Conference_Location :
Belgrade
Print_ISBN :
978-1-4799-6779-7
DOI :
10.1109/DDECS.2015.56
