Author :
Kho, R. ; Boursin, D. ; Brox, M. ; Gregorius, P. ; Hoenigschmid, H. ; Kho, B. ; Kieser, S. ; Kehrer, D. ; Kuzmenka, M. ; Moeller, U. ; Petkov, P. ; Plan, M. ; Richter, M. ; Russell, I. ; Schiller, K. ; Schneider, R. ; Swaminathan, K. ; Weber, B. ; Weber,
Abstract :
In this paper, a 7 Gb/s/pin 1 Gb GDDR5 DRAM with an array architecture for fast column access, a boosting transmitter, multiple voltage (V|NT) domains to control on chip power noise, and a high-speed internal VINT power generator system are presented. This 1Gb GDDR5 memory device is fabricated in a conventional 75 nm DRAM process and characterized for a 7Gb/s/pin data transfer rate at 1.5 V. To achieve fast column-column access times, array improvements are necessary.
Keywords :
DRAM chips; integrated circuit design; integrated circuit noise; DRAM; GDDR5 graphic memory device; bandwidth-improvement technique; bit rate 7 Gbit/s; boosting transmitter; data transfer rate; master column-select lines; multiple voltage domain; on chip power noise; power generator system; size 75 nm; CMOS technology; Current measurement; Delay effects; Driver circuits; Energy consumption; Graphics; Logic; Random access memory; Repeaters; Switches;
