Title :
A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS
Author :
Lee, Hyun-Woo ; Yun, Won-Joo ; Choi, Young-Kyoung ; Choi, Hyang-Hwa ; Jong-Jin Lee ; Kim, Ki-Han ; Kang, Shin-Deok ; Yang, Ji-Yeon ; Kang, Jae-Suck ; Hyeng-Ouk Lee ; Lee, Dong-Uk ; Sim, Sujeong ; Kim, Young-Ju ; Choi, Won-Jun ; Song, Keun-Soo ; Shin, Sang
Author_Institution :
Hynix Semicond., Icheon, South Korea
Abstract :
We design PDLL that has a PLL and a DLL with different roles. The DLL, which is used for phase compensation, is digital with low power consumption. The PLL, which is used for jitter reduction, is a charge-pump type with dual KVCO and self-mode-shifting scheme, using an unregulated power supply for flexibility in operating range. Powering the PLL with an unregulated power supply is made possible by the power-noise- management technique of VPP control and by using a pseudo-rank architecture to suppress VDD noise due to low VPP pumping efficiency.
Keywords :
CMOS integrated circuits; DRAM chips; charge pump circuits; delay lock loops; digital phase locked loops; power supply circuits; CMOS; DLL; GDDR3 DRAM; PLL; bit rate 3.3 Gbit/s; charge-pump circuit; delay-locked loop; dual-mode phase locked loop; jitter control scheme; low power consumption; phase compensation; power-noise-management technique; pseudo-rank architecture; self-mode-shifting scheme; size 54 nm; unregulated power supply; voltage 1.6 V; Active noise reduction; Circuits; Clocks; Delay; Energy management; Frequency; Jitter; Phase locked loops; Power supplies; Random access memory;
Conference_Titel :
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-3458-9
DOI :
10.1109/ISSCC.2009.4977347
