Title :
Increasing Manufacturing Yield Using Partially Programmable Circuits with CLB Implementation of Incompletely Specified Boolean Function of the Corresponding Sub-Circuit
Author :
Matrosova, A. ; Ostanin, S. ; Kirienko, I.
Author_Institution :
Tomsk State Univ., Tomsk, Russia
Abstract :
The new approach to partially programmable circuit design that allows masking arbitrary gate faults of a logical circuit is considered. It is supposed that only one gate may be fault. There are reserved Configurable Logic Blocks (CLBs) based on Look Up Tables (LUTs) that may mask a gate fault. The suggested approach in comparison with the currently in use ones allows masking any gate fault but not the certain stuck at faults at the gate poles.
Keywords :
Boolean functions; logic design; logic testing; programmable circuits; table lookup; CLB implementation; LUT; arbitrary gate fault masking; configurable logic blocks; gate poles; incompletely-specified Boolean function; logical circuit; look up tables; manufacturing yield improvement; partially-programmable circuit design; stuck-at faults; Boolean functions; Circuit faults; Combinational circuits; Data structures; Logic gates; Multiplexing; Programmable circuits; incompletely specified Boolean functions; partially programmable circuit; stuck-at faults; test patterns;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2015 IEEE 18th International Symposium on
Conference_Location :
Belgrade
Print_ISBN :
978-1-4799-6779-7
DOI :
10.1109/DDECS.2015.64
