DocumentCode
1615790
Title
High Throughput Floating-Point Dividers Implemented in FPGA
Author
Malik, Peter
Author_Institution
Inst. of Inf., Bratislava, Slovakia
fYear
2015
Firstpage
291
Lastpage
294
Abstract
New high throughput floating-point dividers implemented in FPGA based on different fast computation division algorithms are proposed. The hardware implementations uses 32-bit floating-point single precision. The implementations include both multiplicative inverse and division. The proposed hardware implementations are designed with high computation speed and throughput. They are oriented for high computation demanding applications with multiple division computations in short sequences.
Keywords
dividing circuits; field programmable gate arrays; floating point arithmetic; FPGA; fast computation division algorithm; field programable gate array; high throughput floating-point divider; multiplicative inverse; word length 32 bit; Computational modeling; Field programmable gate arrays; Hardware; Signal processing algorithms; Standards; Table lookup; Throughput; FPGA; HPC; IEEE 754; dedicated hardware; divider; floating-point;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2015 IEEE 18th International Symposium on
Conference_Location
Belgrade
Print_ISBN
978-1-4799-6779-7
Type
conf
DOI
10.1109/DDECS.2015.66
Filename
7195715
Link To Document