A 130mW 100MS/s pipelined ADC with 69dB SNDR enabled by digital harmonic distortion correction

A pipelined ADC is presented with 2 fully integrated digital background calibration techniques: harmonic distortion correction (HDC) to compensate for residue amplifier gain error and nonlinearity, and DAC noise cancellation (DNC) to compensate for DAC capacitor mismatches. It is the first IC implementation of HDC, and the results demonstrate that HDC and DNC together enable reductions in power dissipation relative to comparable conventional state-of-the-art pipelined ADCs.