Cost of ownership/yield enhancement of high volume immersion lithography utilizing topcoat-less resists

From the initial stages of immersion lithography development, through mainstream manufacturing today, topcoat processes have been utilized. However, the complexity and extra cost associated with the topcoat layer has motivated the industry as a whole to transition to topcoat-less (TC-less) resist processes. By switching to TC-less resists, track suppliers are able to achieve higher throughput using smaller and less costly equipment. In addition, scanner suppliers can increase the scanning speed of their litho scanners with minimized risk of defects, while end-users will eliminate a process step and gain increased output at a lower cost. These factors become increasingly critical as a result of the heightened processing complexities associated with the introduction of double patterning (DP) lithography. Although the motivations for topcoat-less processing are significant, there are numerous technical challenges. One is the potential for added defects, and the correlation between dynamic receding contact angle (D-RCA) and defectivity performance will be discussed. In addition, due to continuous pattern size shrinkage, smaller defects that may not have been problematic or even existed in the past, now can contribute to yield loss. To better understand the defectivity-generation mechanisms, defect review before and after development is necessary. Detailed results of these experiments will also be discussed in this paper. In addition to having defectivity benefits, a topcoat-less process must also satisfy the other critical performance criteria. Results for overlay, autofocus, and imaging will be discussed in this paper. To justify transition to a new technology, there also should be demonstration of associated cost reduction or productivity improvements, and a comparison of topcoat and topcoat-less processes will again be shown.