Title :
A synthesis algorithm for orthogonally structured gate matrix layouts
Author :
Lakhani, Gopal ; Mahendra, Vinay
Author_Institution :
Texas Tech. Univ., Lubbock, TX, USA
Abstract :
The authors discuss a gate matrix layout partitioning problem. To improve the device density in the layout, they present a new template for gate matrix style layouts so that the gates in two adjoining sections of the partitioned layout are orthogonal to each other. The advantages of column folding are included in the template. The simulated annealing technique is used for obtaining the most efficient partition. The implementation of the algorithm is capable of synthesizing large circuits. Experimental results of two examples are given
Keywords :
circuit layout CAD; integrated circuit technology; logic CAD; logic arrays; simulated annealing; column folding; gate matrix layouts; layout partitioning problem; orthogonally structured; simulated annealing; synthesis algorithm; template; Circuit simulation; Circuit synthesis; MOS devices; MOSFETs; Partitioning algorithms; Prototypes; Simulated annealing;
Conference_Titel :
Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-0510-8
DOI :
10.1109/MWSCAS.1992.271086
