A synthesis algorithm for orthogonally structured gate matrix layouts

The authors discuss a gate matrix layout partitioning problem. To improve the device density in the layout, they present a new template for gate matrix style layouts so that the gates in two adjoining sections of the partitioned layout are orthogonal to each other. The advantages of column folding are included in the template. The simulated annealing technique is used for obtaining the most efficient partition. The implementation of the algorithm is capable of synthesizing large circuits. Experimental results of two examples are given