Title :
A 9b 14µW 0.06mm2 PPM ADC in 90nm digital CMOS
Author :
Naraghi, Shahrzad ; Courcy, Matthew ; Flynn, Michael P.
Author_Institution :
Univ. of Michigan, Ann Arbor, MI, USA
Abstract :
As CMOS dimensions scale down, time-domain resolution of digital signals improves but the voltage resolution of analog signals degrades. In this paper, we introduce an ADC architecture based on pulse position modulation (PPM), which relies more on time resolution than on amplitude resolution. In PPM a continuous-time comparator compares the input signal with a voltage ramp. The time interval between the ramp starting point, which is synchronous with the reference clock, and the instant the input signal crosses the ramp is measured by a 2-step time-to-digital converter. Assuming the ramp slope is constant, we can calculate the input-signal amplitude from the measured time vector.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; comparators (circuits); pulse position modulation; 2-step time-to-digital converter; ADC architecture; PPM ADC; continuous-time comparator; digital CMOS; power 14 muW; pulse position modulation; size 90 nm; time vector measurement; time-domain resolution; word length 9 bit; Clocks; Counting circuits; Delay lines; Energy consumption; Flip-flops; Signal generators; Signal resolution; Switches; Time measurement; Voltage;
Conference_Titel :
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-3458-9
DOI :
10.1109/ISSCC.2009.4977361
