Title :
A 1.2V 2MHz BW 0.084mm2 CT ΔΣ ADC with −97.7dBc THD and 80dB DR using low-latency DEM
Author :
Huang, Sheng-Jui ; Lin, Yung-Yu
Author_Institution :
MediaTek, Hsinchu
Abstract :
In this paper, a multi-bit SC DAC is used to improve the stable input range. A low-latency DEM is introduced to minimize quantization-to-DAC delay and to relax OTA BW requirements. The ISI-free RZ coding and reduced internal signal swings contribute to -97.7 dBc THD from a 1.2 V supply.
Keywords :
AC-AC power convertors; delays; quantisation (signal); ISI-free RZ coding; OTA BW requirement; frequency 2 MHz; internal signal swing; low-latency DEM; multibit SC DAC; quantization-to-DAC delay; voltage 1.2 V; Capacitors; Circuits; Clocks; Feedback; Frequency; Jitter; Loss measurement; Stability; Switches; Tail;
Conference_Titel :
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-3458-9
DOI :
10.1109/ISSCC.2009.4977363
