Performance of a fast analog VLSI implementation of the DFT

A fast, analog implementation of the discrete Fourier transforms and inverse discrete Fourier transforms (DFT/IDFTs) requires solutions to the problems of input/output (I/O) bottleneck encountered by large, parallel input sequences, the slow execution time of long sequential sequences, and the resultant error. The authors present an architecture based on several modifications to G. Goertzel´s algorithm (GA) (1958) that provides balances between input serialization, circuit area, execution time, and output error. Such an implementation of a DFT/IDFT based on GA requires only four multipliers, three adders, and two sample and hold circuits