A multirate 3.4-to-6.8mW 85-to-66dB DR GSM/bluetooth/UMTS cascade DT ΔΣM in 90nm digital CMOS

The main advantages of discrete-time (DT) systems are their robustness and their ability to exploit the high switching speeds of transistors in scaled technologies. Operating in discrete time also allows for system reconfiguration by changing the sampling frequency. Moreover, different sampling frequencies can be applied throughout a system. This multirate feature can then be exploited to trade performance for power and flexibility. The multirate technique can also be of benefit to discrete-time DeltaSigma modulators. In DeltaSigma modulators, the first integrators are the largest contributors to the overall power consumption since they set the overall noise and distortion of the modulator. The multirate technique can then be used to reduce the sampling speed of the first integrators and hence the power and compensate for loss in resolution by increasing the speed of the last integrators. However, multirate processing inside a single-loop DeltaSigma modulator introduces additional complexity due to the feedback from the last integrators to the input operating at a lower sampling frequency. This complexity can be avoided by using a cascaded architecture in which the sampling frequency is modified between the stages. It can be shown that a cascade DeltaSigma with the first loop operating at fs/2 and the second loop at 2fs is equivalent in terms of resolution to a cascade DeltaSigma with both loops operating at fs. Furthermore, a cascaded implementation can offer a power-efficient implementation in a multimode context by switching off the appropriate last stages . In this paper we present a 90 nm CMOStri-mode DT multirate cascade DeltaSigma modulator.