Asynchronous circuit verification: From specification to circuit

System development life cycle (SDLC) is currently used widely in systems engineering, information systems and software engineering all over the world. Its variety allows not only software engineers but also computer engineers to apply this process in hardware design. On the hardware side, asynchronous circuits were emerged decades ago when they overcame the clock distribution problem, the main drawback of synchronous circuits. However, there are only a few EDA tools as well as methods for designing and verifying the correctness of the produced circuits. This work is to propose a SDLC approach for asynchronous circuits that enables engineers to describe the desired circuit behaviors and refine those descriptions towards until the target circuits have been conducted. It also allows engineers to verify the circuits formally. The improvement of synthesized environment named PAiD for asynchronous circuits will also be described.