DocumentCode
1616110
Title
A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate
Author
Lee, Seon-Kyoo ; Kim, Young-Sang ; Ha, Hyunsoo ; Seo, Younghun ; Park, Hong-June ; Sim, Jae-Yoon
Author_Institution
Pohang Univ. of Sci. & Technol., Pohang
fYear
2009
Firstpage
184
Abstract
This paper presents a 650Mb/s-to-8Gb/s referenceless CDR with an automatic tracking of data-rate. With a DLL-based frequency acquisition, the presented dual-loop CDR shows the highest performance in lock-range, power consumption, and size compared with previously reported continuous-rate CDRs.
Keywords
clock and data recovery circuits; clocks; digital phase locked loops; DLL-based frequency acquisition; bit rate 650 Mbit/s to 8 Gbit/s; data rate automatic acquisition; dual-loop CDR; power consumption; referenceless CDR circuit; Bit rate; Clocks; Delay; Frequency locked loops; Jitter; Phase detection; Phase frequency detector; Pulse generation; Solid state circuits; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location
San Francisco, CA
Print_ISBN
978-1-4244-3458-9
Type
conf
DOI
10.1109/ISSCC.2009.4977369
Filename
4977369
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