Real time architecture for vector quantization in residue number system

A fast and simplified systolic array architecture for real-time implementation of vector quantization is proposed. The proposed architecture uses the residue number system (RNS) for arithmetic operations. The arithmetic operations can be precomputed and stored in the lookup tables, and the computation time of the arithmetic operations is the access time of the lookup table. The proposed architecture is capable of generating a codevector index each clock cycle with exhaustive search of codebook. A memory-intensive RNS implementation of the systolic array architecture is proposed