Title :
Extending on-die wiring hierarchy with wafer level packaging concepts
Author :
Balachandran, J. ; Brebels, S. ; Carchon, G. ; Webers, T. ; De Raedt, W. ; Nauwelaers, B. ; Beyne, E.
Author_Institution :
Microwave & RF Syst. Group, IMEC, Leuven, Belgium
Abstract :
Wafer level package (WLP) redistribution layer interconnects can be effectively used for countering on-die global wiring challenges. To demonstrate this, we fabricated WLP test chips with two configurations namely IMPS and microstrip transmission lines in WLP layers. Experimental results indicate superior electrical performance. Near speed of light propagation is observed with insignificant signal distortion. We compare the WLP layers interconnect performance with a representative 70nm node upsized global interconnect. Details on the WLP technology are also provided.
Keywords :
integrated circuit interconnections; integrated circuit packaging; transmission lines; wiring; 70 nm; IMPS; WLP layers; WLP test chips fabrication; global interconnect; interconnect performance; microstrip transmission lines; on-die global wiring; propagation speed; redistribution layer interconnects; signal distortion; wafer level packaging; Delay; Electric resistance; Packaging; Power distribution; Radio frequency; Repeaters; Voltage; Wafer scale integration; Wire; Wiring;
Conference_Titel :
Interconnect Technology Conference, 2004. Proceedings of the IEEE 2004 International
Print_ISBN :
0-7803-8308-7
DOI :
10.1109/IITC.2004.1345705
